As a semiconductor device is highly integrated, a lot of research for structures in which a plurality of transistors are multi-stacked within a limited area of a semiconductor substrate has been conducted. A static random access memory (SRAM) device, for example, is one of the semiconductor devices employing a stacked structure of transistors.
FIG. 1 is an equivalent circuit diagram of a conventional inverter.
Referring to FIG. 1, a gate electrode of a first transistor TR1, e.g., an n-channel metal oxide semiconductor (NMOS) transistor, and a gate electrode of a second transistor TR2, e.g., a p-channel MOS (PMOS) transistor, are commonly connected to an input signal Vin line. A source of the second transistor TR2 is connected to a power voltage VDD line, and drains C of the second transistor TIC and the first transistor TR1 are connected to an output line Vout. A source of the first transistor TR1 is connected to a ground voltage VSS line. The device having the above circuit structure may operate as a typical inverter.
The inverter of FIG. 1 may be formed by arranging the first and second transistors TR1 and TR2, of which conductive types are different from each other, on the same plane. However, for high integration of the device, it may be better to configure the inverter as the stacked structure where the second transistor TR2 is stacked on the first transistor TR1.
FIG. 2 is an equivalent circuit diagram of a conventional full CMOS (Complementary Metal-Oxide Semiconductor) SRAM device.
Referring to FIG. 2, the conventional full CMOS SRAM device is configured with two inverters and two transfer transistors TR3 and TR6. The inverters are configured with driving transistors TR1 and TR4, e.g., NMOS transistors, and load transistors TR2 and TR5, e.g., PMOS transistors, wherein the two inverters are cross-coupled to each other. A source of each load transistor TR2 and TR5 is connected to a power voltage VDD line, and a source of each driving transistor TR1 and TR4 is connected to a ground voltage VSS line. Gate electrodes of the transfer transistors TR3 and TR6 are connected to a word line, and one of source/drain thereof is connected to a bit line BL and BL. The other one of the source/drain of each transfer transistor TR3 and TR6, a drain of each driving transistor TR1 and TR4, and a drain of each load transistor TR2 and TR5 are commonly connected to each of common terminals/contacts C1 and C2. In addition, the common terminal C1 is connected to the gate electrode of the driving transistor TR4 and the gate electrode of the load transistor TR5. Likewise, the common terminal C2 is also connected to the gate electrode of the driving transistor TR1 and the gate electrode of the load transistor TR2.
Although the SRAM device may be formed by arranging the six transistors TR1 to TR6 on the same plane, it may be formed by arranging the driving transistors TR1 and TR4 at a lowermost portion, the load transistors TR2 and TR5 on the driving transistors TR1 and TR4, and the transfer transistors TR3 and TR6 on the load transistors TR2 and TR5, and thus, it is possible to enhance the integration of the device by employing this stacked structure.
In the semiconductor device having the structure of the stacked transistors, the common contact such as the common terminals C1 and C2 may be used to connect the stacked transistors to each other. A method of forming the common contact in the semiconductor device having the stacked transistors will be set forth herebelow.
A plurality of interlayer insulating layers stacked on a semiconductor substrate, and a semiconductor single crystalline layer interposed therebetween, are patterned into a predetermined configuration to thereby form a common contact hole, wherein source/drain regions of a transistor are disposed at a predetermined position of the semiconductor single crystalline layer. Thereafter, a metal layer is conformally formed on the resultant structure and an annealing process is performed so as to form an ohmic layer, e.g., a metal silicide layer, on the semiconductor substrate exposed by the contact hole, and sidewalls of the semiconductor single crystalline layer exposed by the contact hole. Afterwards, a conductive layer is formed over the resultant structure to fill the common contact hole, to thereby form a common contact plug.
The contact resistance of the common contact may be varied with the state of the ohmic layer disposed on the bottom and the sidewall of the common contact. For example, an area of the exposed semiconductor substrate under the bottom of the common contact is different from an area of the exposed semiconductor single crystalline layer at the sidewall of the common contact. There is also difference between the thicknesses of the respective ohmic layers on the bottom and the sidewall of the common contact, in order to optimally drive the device. In detail, if the metal layer with a predetermined thickness is formed on the bottom of the common contact to enable the ohmic layer on the bottom to have an optimized thickness, the metal layer on the sidewall of the common contact may be formed thinly in comparison with the metal layer on the bottom. Otherwise, as illustrated in FIG. 3, a void may form between the semiconductor single crystalline layer and the ohmic layer on the sidewall of the common contact so that the resistance may be increased. On the contrary, if the metal layer with a certain thickness is formed on the sidewall of the common contact to enable the ohmic layer on the sidewall to have an optimized thickness, the ohmic layer on the bottom of the common contact may be formed thickly in comparison with the ohmic layer on the sidewall. Resultingly, as illustrated in FIG. 4, a spike is formed so that a leakage current may occur.